Johnathan Smith

Huawei is going for it in a big way. With the MateTV Max, the Chinese company is unleashing a technological firework display that really packs a punch. a 110-inch screen diagonal, mini LED with RGB zone control, 6000 nits peak brightness and a sound system that can hold its own without a soundbar. What sounds […]

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At the White House this afternoon, President Trump said he was terminating "ridiculously burdensome" fuel economy rules. It's part of a series of changes relaxing or eliminating rules promoting cleaner cars.

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Micron announced today that it will exit its Crucial consumer business, bringing an end to retail sales of Crucial-branded SSDs and memory modules at major stores and online retailers. The company says it will continue shipping Crucial products through fiscal Q2 2026 (ending February 2026), after which the brand will no longer operate in the consumer channel. Warranty coverage and support will remain in place. Micron says the shift is driven by surging AI-related demand in the data center, which requires reallocating manufacturing capacity toward higher-margin enterprise and hyperscale customers. The company noted that its strategic focus is now on segments with stronger long-term growth in memory and storage rather than the competitive consumer market.

Crucial, best known for SSDs like the MX and P-series and its long-running line of desktop and laptop DRAM modules has been part of Micron's portfolio for nearly three decades. While consumer products are being phased out, Micron will continue selling Micron-branded enterprise SSDs and memory through its commercial channels. The company also stated it intends to limit workforce disruption by redeploying affected employees into open internal roles wherever possible. Micron's move comes as demand for AI hardware continues to surge. The company secured major HBM3E contracts with NVIDIA and AMD and expects to sample HBM4 next year.

President Trump has officially pardoned former Honduran President who US officials said was at the center of one of the largest and most violent drug-trafficking conspiracies in the world.

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Israeli Prime Minister Benjamin Netanyahu has asked Israel's president to grant him a pardon during his long-running corruption trial that's bitterly divided the country.

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Food and Drug Administration officials say they will ratchet up requirements for vaccine studies, citing concerns about COVID shots for kids. But public health experts question the agency's analysis.

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According to one of the analysts closest to the Apple supply chain, Ming-Chi Kuo, Intel is expected to manufacture Apple's advanced M-series of chips by 2027. According to Kuo, Apple has used version 0.9.1 of process design kit (PDK) designed for Intel 18AP node. With performance, density, power, and every other metric going according to plan, Intel could become Apple's source of advanced node production in 2027. Additionally, Apple is reportedly waiting for Intel to release 18AP PDK version 1.0 or 1.1, which is scheduled for Q1 of 2026. When that gets released, Apple will start with lowest-end M-series chip, used by MacBook Air and iPad Pro devices.

Interestingly, Intel expected customers to adopt more of the refined 18A nodes—like 18A-P and 18A-PT—and later 14A nodes, than its current vanilla 18A. The 18A-P node enhances Intel's 18A by incorporating RibbonFET and PowerVia technologies, which offer better performance and energy efficiency. Compared to the regular 18A node, these improvements include newly designed low-threshold voltage components, optimized elements to reduce leakage, and refined ribbon width specifications, all aimed at boosting performance-per-watt metrics. Apple's designs are very similar to Intel's "Lunar Lake," which includes compute and memory on a single package. This is made using the "Foveros" advanced packaging, which we covered here.

Yep, you read it right, a smartphone with a subwoofer. Xiaomi launches POCO F8 Ultra powered by Snapdragon 8 Elite Gen-5, featuring Bose-supervised stereo speakers plus a rear-mounted subwoofer, a bright 6.

Qualcomm is finally talking about the tech of their CPUs with the new Snapdragon X2 Elite Extreme CPUs.
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The post A Deep Dive Into The Qualcomm Snapdragon X2 Elite SoC appeared first on Semiaccurate.

The volcano near Naples is shaking the ground in a way that scientists say it hasn't for centuries, posing risks for hundreds of thousands of people living in the 8-mile-wide crater left by past eruptions.

(Image credit: Valerio Muscella for NPR)

Amazon has unveiled Leo Ultra, a high-throughput phased-array terminal for its upcoming satellite internet service, now rebranded from Project Kuiper to Amazon Leo.

Gavin Weisenburg, 21, and Tanner Thomas, 20, planned to take over Gonave Island and murder all men on the island, prosecutors alleged.

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AOC shows off its fresh QD-OLED monitor lineup

Hello you fine Internet folks,

Last week I was in San Diego at Qualcomm’s Headquarters where Qualcomm disclosed more information about their upcoming Snapdragon X2 Elite SOC.

Snapdragon X2 Elite is Qualcomm’s newest SOC for the Windows on ARM ecosystem that is designed to bring a new level of performance so let’s dive in.

Oryon Gen 3 Prime CPU Cores and Cluster

The Snapdragon X2 Elite (SDX2E) comes equipped with a total of 18 CPU cores with 12 “Prime” cores and 6 “Performance” cores.

Starting with the Prime cores, these are the real heart of the SDX2E SoC with a total of up to 12 cores split across 2 clusters that can clock up to 5.0 GHz.

Each of these clusters has 16MB, 16-way associative, shared L2 cache with 6 Prime cores attached along with a Qualcomm Matrix Engine per cluster.

The L2 can serve up to 64B per cycle per core with a total fill bandwidth of up to 256B per cycle for the cluster. The L1 miss to L2 hit latency is now 21 cycles, up from the 17 cycles of the Snapdragon X Elite (SDXE). The reason for this increase is due to the increased size of the structure. The L2 runs at the same clocks as the cores and supports over 220 in-flight transactions with each core supporting over 50 requests to the L2 at a time.

Diving into the CPU cores and there is quite a bit familiar with this core at a high level.

Starting with the L1 instruction cache, it is 192KB in size with 6-way associativity and is fully coherent. The Fetch Unit can fetch up to 16 4 Byte instructions per cycle for a total fetch bandwidth of 64 Bytes per cycle. The L1 iTLB is an 8-way associative, 256 entry structure that supports 4KB and larger page sizes.

Moving to the Decode, Rename, and Retirement stages, Oryon Gen 3 has increased these stages up to 9 wide from the 8 wide that Oryon Gen 1 was meaning that Oryon Gen 3 can support up to 9 micro-ops retired per cycle. There are over 400 Vector and Integer registers in their respective physical register files which is similar to the number of entries in Oryon Gen 1. Similarly, the Reorder Buffer is similarly 650+ entries for Oryon Gen 3.

Delving into the Integer side of the core, Oryon Gen 3 now has 4 Branch units which is a doubling of the number of Branch units found inside Oryon Gen 1. Otherwise, the integer side of Oryon Gen 3 is very similar to Oryon Gen 1 with 6 20-entry Reservation Stations for a total of 120 entries in the Integer scheduler, 6 Integer ALUs with 2 capable of Multiplies and one unit capable of handling Crypto and Division instructions.

Swapping to the Vector unit and Oryon Gen 3 adds SVE and SVE2 support to the core with the high-level layout similar to Oryon Gen 1 with over 400 128b Vector registers, 4 128b Vector ALUs all capable of FMAs, and 4 48-entry Reservation Stations for a total of 192 entries in the Vector scheduler.

Moving to the Load and Store system, Oryon Gen 3 has the same 4 Memory AGUs all of which are capable of loads and stores as Oryon Gen 1. These then feed a 192 entry Load Queue and 56 entry Store Queue which are the same size as the queues found on Oryon Gen 1. The L1 Data Cache is also the same fully coherent 96KB, 6-way. 64 Byte cache line, structure as what Oryon Gen 1 had.

Landing at the Memory Management Unit, and the TLBs of Oryon Gen 3 are again very similar to Oryon Gen 1 with one possible difference. Slide 11 says that the L1 dTLB is a 224 entry, 7-way, structure whereas Slide 12 says that the L1 dTLB is a 256 entry, 8-way, structure. If Slide 12 is correct then this is an increase from Oryon Gen 1’s 224 entry, 7-way, L1 dTLB. Oryon Gen 3’s 256 entry, 8-way, L1 iTLB and 8K entry, 8-way, shared L2 is unchanged from Oryon Gen 1. Note, the 2 cycle access for the L2 TLB is the SRAM access time not the total latency for a TLB lookup which Qualcomm wouldn’t disclose but is a similar range to the ~7 cycles you see on modern x86 cores.

Qualcomm’s Matrix Engine

In each of SDX2E’s 3 clusters lies a SME compatible Matrix Engine.

This matrix unit uses a 64 bit x 64 bit MLA numeric element in a 8x8 or 4x8 grid. This means that this matrix unit is 4096 bit wide which can do up to 128 FP32/INT32, 256 FP16/BF16/INT16, or 512 INT8 operations per cycle. The matrix engine is on a separate clock domain to the Cores and L2 Cache for better power and thermal management of the SoC.

Qualcomm Oryon Gen 3 Performance Core and Cluster

Something that is new to the SDX2E that SDXE didn’t have is a 3^rd cluster on board with what Qualcomm is calling their “Performance cores”.

This cluster has the same number of cores along with the Matrix Engine as the Prime Clusters but instead of 16 MB of shared L2, the Performance Cluster has 12 MB of shared L2.

The Performance core is also different to the Prime cores. These cores are of a similar but distinct microarchitecture to the Prime cores. These cores are targeted at a lower power point and has been optimized for operation below 2 watts. As such, the Performance core isn’t as wide as the Prime core and has fewer execution pipes, smaller caches, and shallower Out-of-Order structures compared to the Prime core.

Adreno X2 GPU

SDX2E has a revamped GPU architecture that Qualcomm is calling the Adreno X2 microarchitecture.

This is Qualcomm’s largest GPU they have made to date with 2048 FP32 ALUs clocking up to 1.85GHz.

The Adreno X2 is a “Slice-Based” architecture, roughly equivalent to a Shader Engine from AMD or a GPC from Nvidia, with 4 slices for the top-end X2-90. Each slice has one Front-End which capable of rasterizing up to 4 triangles per cycle.

After the Front-end, are the Shader Processors, which are roughly equivalent to AMD’s WGP or Nvidia’s SM, which has an instruction cache and 2 micro-Shader Processors (uSP), similar to AMD’s SIMD unit or Nvidia’s SMSP, which each have a 128KB register file feeding 128 ALUs which support FP32, FP16, and BF16. A change from the prior Adreno X1 architecture is the removal of Wave128, now the Adreno X2 only supports Wave64 and can dual issue Wave64 instructions in order to keep the 128 ALUs fed.

Each uSP has a Ray Tracing Unit which supports either 4 ray-triangles or 8 ray-box intersections per cycle.

From there is what is referred to as Adreno High Performance Memory (AHPM). There is 21 MB of AHPM in a X2-90 GPU, 5.25 MB per slice, which is both a scratchpad and a cache depending on what the driver configures it as. Up to 3 MB of each of the 5.25 MB slices can be configured as a cache with the remaining 2.25 MB of SRAM being a scratchpad.

AHPM is designed to allow for the GPU to do tiled rendering all within the AHPM before rendering out the frame to the display buffer. This reduces the amount of data movement that the GPU has to do which consequently improves the performance per watt of the Adreno X2 compared to the Adreno X1.

Moving back to the Slice level, each slice has a 128 KB cluster cache which is then backed by a unified 2 MB L2 cache. This L2 can then spill into the 8 MB System Level Cache (SLC) which then is backed by the up to 228 GB/s memory subsystem.

As for API support, Adreno X2 supports DX12.2, Shader Model 6.8, Vulkan 1.4, OpenCL 3.0, as well as SYCL support coming in the first half of 2026.

Hexagon NPU

Qualcomm has increased the performance of the Hexagon NPU from 45 TOPS of INT8 to 80 TOPS of INT8 with SDX2E.

Qualcomm has also added FP8 and BF16 support to the Hexagon NPU 6 vector unit.

In addition to the BF16 and FP8 support, the new matrix engine in NPU 6 has INT2 dequantization support.

Regulator sides with telcos that claimed new cybersecurity duties were too ‘burdensome’

The Federal Communications Commission (FCC) will vote this week on whether to scrap Biden-era cybersecurity rules, enacted after the Salt Typhoon attacks came to light in 2024, that required telecom carriers to adopt basic security controls.…

It's trendy in some circles to replace drinking with consuming cannabis. But can it help people with a drinking problem cut back? Scientists set up a bar in the lab to find out.

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Intel's John Pitzer, a Vice President in charge of Corporate Planning & Investor Relations, announced that yields for "Panther Lake" on the Intel 18A node have been increasing by approximately 7% each month. At the RBC Capital Markets Global TMT conference, we received an update on Intel Foundry and its developments. This reported growth rate aligns with industry expectations for a healthy ramp-up. After months of reports about poor yields, it's reassuring to see that the yield curve for the 18A node is generally improving, ensuring that Panther Lake chips will be delivered on time. Over the past seven to eight months, the yield curve has shown consistent improvement. If the 7% monthly growth continues, Intel could potentially scale Panther Lake into volume production without significantly increasing per-unit costs. However, the speed at which customers receive chips will depend on the absolute ramp speed and capacity decisions.

John PitzerWe clearly want to do better on the gross margin side. I think what's important is when Lip-Bu joined in March, he was unsatisfied by yields and he was unhappy that the progress on yields was sort of erratic. I think one of the things that's changed dramatically over the last 7 or 8 months, is we now have a predictable path for yield improvement. We've talked about in the past that the industry average yield improvement on a new ramp is about 7% per month. And we are now on that curve for Panther Lake, which is giving us some confidence as we launched the product this quarter. And like I said, if you go to CES in January, you can hear a lot more about that.

Researchers say they believe they've documented the first known death from alpha-gal syndrome — a red meat allergy caused by tick bites.

Intel is simplifying its product stack in the upcoming "Diamond Rapids" Xeon 7 family of processors, and the focus is on memory bandwidth. An Intel spokesperson confirmed for ServeTheHome that the company will be exclusively focusing on 16-channel Xeon 7 CPUs, and that the eight-channel designs have been cancelled. "We have removed Diamond Rapids 8CH from our roadmap. We're simplifying the Diamond Rapids platform with a focus on 16-channel processors and extending its benefits down the stack to support a range of unique customers and their use cases." This is a potential massive advantage for Intel customers across the stack as the added memory bandwidth will increase performance across most workloads.

For servers, Diamond Rapids will use "Panther Cove" P-cores and push core density aggressively. It is expected to arrive in the second half of 2026. The Xeon 7 series will feature up to 192 P-cores in the top-end SKU, split across four 48-core tiles. These initial Panther Cove server chips will not include simultaneous multithreading. However, Intel plans to address this with the follow-up "Coral Rapids" family, which will reintroduce Hyper-Threading for datacenter workloads.

A growing dispute inside one of Europe’s largest chipmakers is threatening to derail automotive production across the continent.

Democrats on the House Oversight Committee have released several emails from the estate of convicted sex trafficker Jeffrey Epstein that refer to President Trump.

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For years, people have warned that fast charging ruins your phone’s battery over time. A recent long-term test from YouTube channel HTX Studio set out to find out if that’s really true — and the results might surprise you.

It sounds a lot like everything else

AI slop has reached a new level of ascendancy, as a country song by an AI artist has hit number one on Billboard's Country Digital Song Sales chart.…

NAND flash prices have surprisingly doubled over the past six months, confirms Phison CEO Khein-Seng Pua. As one of the few executives at the top of the NAND flash supply chain, Pua has insights into the supply and demand dynamics for NAND products. The demand for AI infrastructure has rapidly depleted inventory across the supply chain, and NAND flash is no exception. The swift expansion of AI infrastructure has led to NAND flash shortages, which could continue for years. Pua noted that the price of a 1 Terabit TLC NAND jumped from $4.80 in July 2025 to $10.70 in November 2025, marking an increase of over 100% in less than six months. Other types of NAND flash, such as MLC and QLC, have also seen spot prices more than double.

Recently, CEO Pua mentioned that the NAND flash shortage might persist for an entire decade. In previous cycles, heavy investment often resulted in price collapses, prompting many flash manufacturers to scale back and slow down expansion. Beginning around 2023, a substantial portion of capital was shifted towards high-bandwidth memory used for model training, due to its more attractive profit margins. As a result, NAND received less attention just as demand started to increase again. To manage demand, new NAND flash manufacturing sites are being built. However, Phison CEO claims that new production lines will not go online until 2027, making his older prediction possibly true.

Two Major League Baseball pitchers have been indicted on charges they took bribes to give bettors advance notice of the types of pitches they'd throw and intentionally tossed balls instead of strikes.

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An experimental gene-editing treatment shows promise for permanently lowering levels of cholesterol and triglycerides, possibly helping cut the risk for heart disease.

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A proposal to change the USPTO's fee structure from fixed rates to a percentage basis is facing resistance from the semiconductor industry.

Samsung teases the AM9C1 E1.A Detachable AutoSSD and PM9E1 M.2 22x42 SSDs that will be revealed at CES 2026.

Medicare beneficiaries will soon be able to get obesity and Type 2 diabetes drugs for a $50 copay. But there are some limitations.

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Microsoft is finally fixing something that has annoyed Windows users for years. When you clicked “Update and Shutdown,” your PC didn’t really shut down—it restarted after finishing the updates.